1. Field of the Invention
This invention relates generally to semiconductor fabrication processes, and specifically to analyzing the performance of particular tool and chamber sequences in a semiconductor fabrication process.
2. Description of Background
Processes for fabricating semiconductors often include placing semiconductor wafers in chambers and using tooling processes. As the wafers are fabricated, they are placed in different sets of chambers that each perform a function in the fabrication process. For example, one set of chambers may be used for depositing material on production run of wafers and another set of chambers may be used to etch portions of the material from the wafers. Though each of the chambers in a set may be calibrated to perform an operation within a given range of tolerances, each chamber may still have a variance in the output from the process that is within the tolerance. The variances may have an additive effect on the output of the production run of wafers. For example, if a wafer is run through a chamber that deposits material on the wafer at a lower end of a deposition tolerance, the wafer will have a thinner layer of material. If the wafer is then run through a chamber that etches material at a higher end of an etching tolerance, the resultant layer of material may be outside of the specifications for the finished wafer.